1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device having a test mode in which the voltages of a plurality of word lines are boosted simultaneously. More particularly, the present invention relates to a configuration for performing a burn-in test at a wafer level.
2. Description of the Background Art
In recent years, semiconductor devices in which a large number of transistors are integrated have been used for various electric equipments such as a workstation and a personal computer. In manufacturing semiconductor devices, it is necessary for reliability testing and defect screening to perform a xe2x80x9cburn-inxe2x80x9d for operating and testing a semiconductor device in a high temperature range with a voltage higher than a normal operation voltage applied to the power supply of the semiconductor device. Because of stress caused by the burn-in, a potential defect portion which is latent in an insulation film or the like included in the semiconductor device is acceleratingly deteriorated and rendered revealing. Thus, the defective semiconductor device can be screened. The known burn-in tests includes a burn-in test carried out after semiconductor chips are assembled into a package, and a wafer level burn-in (WBI) test carried out on a wafer having a plurality of semiconductor chips which are not assembled yet.
The wafer level burn-in test is described, for example, by T. Furuyama et al., in xe2x80x9cWafer Burn-In (WBI) Technology for RAM""s,xe2x80x9d 1993 IEDM Tech. Digest, pp.639-642. The wafer level burn-in test has the following advantages over the conventional burn-in test. First, a semiconductor chip is not sealed in a package or a mold. It is therefore possible to perform the burn-in at a temperature higher than the tolerable (heat-resistant) temperature of the package or the mold. In addition, the burn-in voltage can be applied externally through a pad. It is therefore possible to set a higher stress electric field to shorten the burn-in time. Secondly, the wafer burn-in test is performed before a repair test for replacing a defective bit with a redundant one by laser trimming or the like. It is therefore possible to repair a defect, which is caused after the burn-in, by a subsequent repair test, improving the manufacturing yield. Thirdly, the location of a semiconductor chip with a detected defect on a wafer can be checked. By feeding back the defect information to the manufacturing line, the cause of the defect is eliminated at a wafer level and the manufacturing process can be improved easily.
A DRAM (Dynamic Random Access Memory) has memory cells each formed of one transistor/one capacitor, is inexpensive per bit, and has a structure suitable for high density. Therefore, the DRAM is utilized as a main memory for a personal computer that requires a large memory capacity. In the DRAM, the memory cells are arranged in rows and columns and each cell stores one-bit information of xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. One electrode of a memory cell capacitor is formed of a cell plate and supplied with a prescribed voltage (intermediate voltage xc2xd times as high as an array power supply voltage). A plurality of word lines are provided for the rows of the memory cells, and a plurality of bit line pairs are provided for the columns of the memory cells. A gate of a memory cell transistor is connected to a corresponding word line (the memory cell transistor is usually a MOS transistor, and gate electrodes and word lines are formed in the same interconnection layer). The memory cell transistor is connected between a corresponding bit line and the other electrode (storage node) of the memory cell capacitor.
In the wafer level burn-in test, all the word lines are simultaneously selected or every other word lines are simultaneously selected in a stripe manner, and the bit lines and the cell plates are externally supplied with voltages. With the external burn-in voltage, a stress voltage can be applied to the gate insulation film of a memory cell transistor, the insulation film of a memory cell capacitor, an insulation film between adjacent word lines, an insulation film between adjacent memory cells, and so on.
FIG. 1 shows a configuration of a word line drive portion in a conventional DRAM described, for example, in U.S. Pat. No. 5,513,142. In the configuration shown in FIG. 1, a word line drive circuit for driving a corresponding word line to a selected state in accordance with a word line selection signal ZWD and sub decode signals RXi and ZRXi are provided for each word line WL. Sub decode signal RXi is generated by a boost signal driver RXD which receives the decode result RXF of a prescribed number of bits of a row address. Boost signal driver RXD receives, as one operating power supply voltage, a boosted voltage Vpp higher than an array power supply voltage. Sub decode signal ZRXi is generated by an inverter INV which receives sub decode signal RXi from boost signal driver RXD. Inverter INV is formed of a CMOS inverter and receives, as one operating power supply voltage, an array power supply voltage Vcca, not shown.
Word line drive circuit DRV includes a P channel MOS transistor P1 connected between a node receiving sub decode signal RXi and a corresponding word line and receiving word line selection signal ZWD at its gate, an N channel MOS transistor N1 connected between a corresponding word line and a ground node and receiving corresponding word line selection signal ZWD at its gate, and an N channel MOS transistor N2 connected between the ground node and corresponding word line WL and receiving a complementary sub decode signal ZRXi at its gate.
Boost signal driver RXD is provided commonly to 128 word lines WL, for example. In wafer level burn-in, word line selection signals ZWD simultaneously attain a selected state or a low level, sub decode signal RXi from boost signal driver RXD attains the boosted voltage Vpp level, and complementary sub decode signal ZRXi becomes a low level. In each of word line drive circuits DRV, P channel MOS transistor P1 is rendered conductive while N channel MOS transistors N1 and N2 are rendered non-conductive, so that sub decode signal RXi at the boosted voltage Vpp level is transmitted onto each word line WL. In short, a plurality of, for example 128, word lines WL are driven simultaneously to the selected state by one boost signal driver RXD. However, the drivability of boost signal driver RXD is designed to drive one word line from a ground voltage GND to boosted voltage Vpp at a certain speed in a normal operation mode. If boost signal driver RXD comes to have unnecessarily large drivability in the normal operation mode, the power consumption in the normal operation mode and the occupied area by the driver are increased, and therefore the drivability of boost signal driver RXD is set at a necessary minimum value. Therefore, when 128 word lines WL are to be driven simultaneously to the selected state in the wafer level burn-in test, boost signal RX gradually rises and exceeds the input logic threshold of inverter circuit INV. If boost signal RXi rises gradually as shown in FIG. 2, the falling speed of complementary sub decode signal ZRXi from inverter circuit INV becomes slower. In other words, shortly before the voltage level of sub decode signal RXi exceeds input logic threshold VIT of inverter circuit INV, complementary sub decode signal ZRXi begins to fall, and the voltage level of complementary sub decode signal ZRXi gradually becomes low as the voltage level of sub decode signal RXi rises.
Complementary sub decode signal ZRXi is applied to the gate of N channel MOS transistor N2 in word line drive circuit DRV. MOS transistor N2 is turned off when the gate-to-source voltage becomes a threshold voltage Vth or lower. Therefore, when the voltage level of sub decode signal RXi rises gradually, there is a period during which MOS transistor N2 is on in word line drive circuit DRV, and electric charges from boost signal driver RXD are discharged to the ground node through 128 word line drive circuits DRV. As a result, the voltage level of word line WL does not rise to the boosted voltage Vpp level, but is saturated at a level around input logic threshold VIT of inverter circuit INV. The input logic threshold of inverter circuit INV may deviate from a set value and become higher due to variation in the manufacturing process, for example. In such a case, N channel MOS transistor N2 for discharging word line drive circuit DRV maintains its on state, and most of the charge current from sub decode signal RX at the boosted voltage Vpp level to word line WL is discharged to the ground node. Consequently, it is impossible to transmit boosted voltage Vpp to word line WL and accurately perform the burn-in at a wafer level.
N channel MOS transistor N2 is provided for the reasons described below. When word line selection signal ZWD and sub decode signal RXi are both at the low level, MOS transistors P1 and N1 are both off. At this time, corresponding word line WL enters an electrically floating state, and the voltage level is fluctuated due to noises. That may affect adjacent word lines. In order to prevent the word line from shifting to the floating state, MOS transistor N2 is turned on by complementary sub decode signal ZRXi so as to maintain the word line at the ground voltage GND level. Therefore, MOS transistor N2 is provided to guarantee regular word line selection operation in the normal operation mode, and therefore MOS transistor N2 cannot be removed.
An object of the present invention is to provide a semiconductor memory device capable of reliably driving a selected word line to a boosted voltage Vpp level in a wafer level burn-in mode.
In summary, a semiconductor memory device according to the present invention generates a signal for driving a transistor, which is provided to prevent a word line from entering a floating state, from a sub decode signal at a boosted voltage level and a voltage acceleration mode designation signal which in turn is activated in a wafer level burn-in mode.
More specifically, the semiconductor memory device according to the present invention includes a boost signal generator for generating a sub decode signal at the boosted voltage level, a drive signal generator for generating a drive signal complementary to the sub decode signal in accordance with the sub decode signal and the voltage acceleration mode designation signal that is activated in the wafer level burn-in mode, a plurality of word lines each provided for a memory cell row and connected to memory cells in a corresponding row, and word drivers provided corresponding to the plurality of word lines for driving corresponding word lines to a selected state in accordance with at least the sub decode signal and the drive signal. Each of the plurality of word driver includes a first drive transistor for transmitting, when conductive, the sub decode signal to a corresponding word line, and a second drive transistor rendered conductive in response to the drive signal for fixing, when conductive, a corresponding word line to a low level reference potential.
Since the drive signal is generated from the sub decode signal and the voltage acceleration mode designation signal, even if the sub decode signal rises to the boosted voltage level, the drive signal can be changed at a high speed in accordance with the voltage acceleration mode designation signal and the first and second transistors can be prevented from being rendered conductive at the same time in the word driver. Thus, a plurality of word lines which are selected simultaneously can be driven reliably to the boosted voltage level.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.